The 16F87X PICs have a 10 Bit successive approximation A to D converter with a switched capacitor sample and hold input. This can be time multiplexed into up to 8 separate channels by a software selectable multiplexing switch. There is the capability to use an internal 5V voltage reference or an external one with a user selected voltage.
The datasheet details the sample rate considerations for the A/D. The conversion time divides up into three distinct sections.
This relates to the sample and hold circuits response to a step change in input voltage. As a result this is mainly of significance when the A/D is used in multiplexed mode. The minimum acquisition time is controlled by the impedance of the analog source.
Tacq = Amplifier settling time + Hold capacitor charging time + Temperature coefficient. [I'll be ignoring temperature effects throughout, assuming operation at 25C]
Tacq = 2us + Chold(Ric+Rss+Rs)*abs(ln(1/2*1/(2^n))) , where n is the number of bits and 1/2 is the required accuracy in bits.
Tacq = 2us +120E-12*(8E3+Rs)*7.624
This is the time the A/D converter takes to make the conversion. This is (2+n)Tad,where n is the number of bits of resolution (max 10 on 16F87X) Tad is a minimum of 1.6us on 16F87X giving a minimum conversion time of 20us. However Tad is derived from a clock on the PIC so that at 4Mhz the smallest Tad available is 2us, giving a minimum conversion time of 24us for 10 bits of resolution.
This is the time between the conversion completing and the sampling switch closing again and the next acquisition being able to start.
This is 2Tad or 4us min on a 4Mhz system.
Overall therefore the maximum sample rate on a 4Mhz system with a 10K input impedance is 19us +24us+4us =47us = 21kHz.
I have constructed the following SPICE model of the A to D input based on the diagram of the equivalent circuit given in the Microchip datasheet.
*PIC 16FXXXX 10 bit A/D Input Model
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SPICE simulator plot giving an illustration of the holding capacitor Chold charging during the A/D acquisition time.
It is generally regarded as good practice to put a low pass filter on to an A/D input to prevent noise and aliasing problems.
The simplest filter is an RC network applied to the A/D input. As noted above the input impedance has an effect on the length of time to charge the holding capacitor (Tacq). In addition in the worst case where adjacent channels have widely differing
voltages a significant mean current may be drawn due continuously having to charge the sample capacitor. This mean current is directly proportional to the sample rate.
In the worst case where the sampling capacitor is required to be charged from 0 to 5v the charge required is
Q= CV = 120E-12*5 = 600E-12 Coulombs
This charge may be required for each acquisition therefore developing a current flow proportional to the sampling rate. The maximum mean current flow at 20000 samples per second is 12uA. Averaged out this is equivalent to a 120mV drop across a 10K input resistor, at approximately 5mV per bit this will cause an significant error of 24 counts. As the current should only flow during the acquisition phase of the conversion the error will only become apparent if the time constant of the input filter is longer than the acquisition time - which is exactly what we need for antialiasing. Thus to keep the error within budget we need to limit the maximim value of the input resistor to a value derived from the sample rate.
The calculation for Rin as follows:
Rin = Vemax/Is
where Vemax is the maximum allowed error voltage and Is is the sampling current.
Is = Srate*Chold*Vmax
where Is is the sampling current.
=>
Rin = Vemax/(Vmax*Srate*Chold)
= Vemax/Vmax/Srate/Chold
Some example values:
| Rate (1/s) | Rin Max (ohms) |
| 10 | 407k |
| 100 | 40.7k |
| 1000 | 4.07k |
| 10000 | 407 |
Copyright Andrew Ferry 2004.