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Wearwulf

Processor Resources

Communications (UART0)

No.	Name	Use	Description
13	P0.0/TxD0/PWM1	TxD0	Transmitter output
14	P0.1/RxD0/PWM3	RxD0	Receiver input
18	P0.2/SCL/CAP0.0	P0.2	Cable in-use
44	P0.14/DCD1/EINT1	P0.14	In-circuit programming mechanism

Pin P0.18 is a logic '1' level whenever a valid RS232 level is present from the PC. The Wearwulf can periodically check this pin to determine whether an external serial device has been connected, and act appropriately.

Pin P0.14 should be pulled low for at least 3ms after the LPC2106 is reset in order to enter in-circuit programming mode. This is achieved manually using an external jumper.

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Serial Peripheral Interface (SPI)

The SPI interface will be used to connect both the Geek Port (Atmel ATmega/8L), and the MMC mass storage device. (As SSEL can no longer be used for PWM2, some restructuring of the video interface was necessary.)

No.	Name	Use	Signal	Description
22	P.4/SCK/CAP0.1	SCK	SCK	Serial clock
23	P0.5/MISO/MAT0.1	MISO	MISO	Master In Slave Out
24	P0.6/MOSI/CAP0.2	MOSI	MOSI	Master Out Slave In
28	P0.7/SSEL/PWM2	SSEL	SSEL	Must be held inactive

To select one or the other device, then two separate chipselects are required if we want to ensure both devices can be deselected.

No.	Name	Use	Signal	Description
15	P0.30/TRACEPKT3/TDI	P0.30	MMC*	MMC select
16	P0.31/EXTIN/TDO	P0.31	GEEK*	Geek Port select

The Geek Port coprocessor will be able to interrupt the LPC2106 via the ALRM^* alarm signal, enabling it to warn the processor when battery failure are imminent. In addition, the LPC2106 will be able to hold the ATmega/8L in reset, allowing it to be reprogrammed in-system via its SPI interface.

No.	Name	Use	Signal	Description
45	P0.15/RI1/EINT2	EINT2	ALRM*	Geek Port interrupt
48	P0.18/CAP1.3/TMS	P0.18	GRES*	Geek Port reset

Even though the SPI interface is operated in master mode, the SSEL pin must be used and held inactive. Failure to do so will cause a Mode Fault to be generated, and SCK, MOSI and MISO pins will be inactive.

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Display Interface

No.	Name	Use	Signal	Description
29	P0.8/TxD1/PWM4	PWM4	HPL*	Horizontal Pulse
3	P0.21/PWM5/TDO	PWM5	ODD*	Odd row
30	P0.9/RxD1/PWM6	PWM6	MARK3	Asserts at 3rd clock
37	P0.12/DSR1/MAT1.0	MAT1.0	FRAMEM3	Toggles 3 clocks before FRAME
1	P0.19/MAT1.2/TCK	MAT1.2	FRAME	Toggles every frame
2	P0.20/MAT1.3/TDO	MAT1.3	FRAMEP6	Toggles 6 clocks after FRAME
47	P0.17/CAP1.2/TRST	P0.17	PDR*	Power down request
41	P0.13/DTR1/MAT1.1	P0.13	PWR*	Switch off power supply. !!
46	P0.16/EINT0/MAT0.2	EINT0	EMPTY	Video queue empty
32	P0.22/TRACECLK	P0.22	VDAT0	Video data (bit 0)
33	P0.23/PIPESTAT0	P0.23	VDAT1	Video data (bit 1)
34	P0.24/PIPESTAT1	P0.24	VDAT2	Video data (bit 2)
38	P0.25/PIPESTAT2	P0.25	VDAT3	Video data (bit 3)
39	P0.26/TRACESYNC	P0.26	VDAT4	Video data (bit 4)
8	P0.27/TRACEPKT0/TRST	P0.27	VDAT5	Video data (bit 5)
9	P0.28/TRACEPKT1/TMS	P0.28	VDAT6	Video data (bit 6)
10	P0.29/TRACEPKT2/TCK	P0.29	VDAT7	Video data (bit 7)
36	P0.11/RTS1/CAP1.1	P0.11	VWR*	Video write

Using a clock rate of 6MHz:

• Action(s) per row (every 336 clocks):
• ODD^* toggles at the end of each row.
• MARK3 asserts at 3rd clock.
• HPL^* is low between the 335.5th clock and the 0.5th clock.
• Action per frame (every 80640 clocks):
• FRAME toggles at the end of each frame.
• FRAMEM3 toggles 3 clocks before the end of each frame, initially '1'.
• FRAMEP6 toggles at the 6th clock after each frame, initially '0'.
• Logic combinations:
• MARK6 is generated from MARK3 (using 3 shift registers).
• VPL^* is '0' when FRAMEM3!=FRAMEP6, otherwise '1'.
• HODL is ODD^* when FRAME^*='0', NOT(ODD^*) when FRAME^*='1'.
• VCK^* is MARK3 when ODD^*='0', otherwise '1'.
• RENE^* is MARK6 when ODD^*='0', otherwise '1'.
• RENO^* is MARK6 when ODD^*='1', otherwise '1'.

The clock rate will actually be 12MHz, and halved within the CoolRunner II logic. This will allow actions on both clock edges of the '6MHz' clock (necessary for HPL^*). The CoolRunner II and Philips LPC2106 will share the same clock generator to save costs - the Philips LPC2106 will then convert this lower frequency up to the 60MHz clock frequency that it can operate at.

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General Purpose pins (UNUSED)

No.	Name	Use	Description
21	P0.3/SDA/MAT0.0	P0.3	Unused
35	P0.10/CTS1/CAP1.0	P0.10	Unused

There are only a few general purpose digital i/o pins remaining unused - this might be a problem if it wasn't for the presence of the Atmel ATmega/8L coprocessor as a Geek Port. These pins have been retained for future expansion.

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